As semiconductor technology continues to inch closer to practical limitations in terms of increases in clock speed, architects are increasingly focusing on parallelism in processor architectures to obtain performance improvements. At the chip level, multiple processor cores are often disposed on the same chip, functioning in much the same manner as separate processor chips, or to some extent, as completely separate computers. In addition, even within cores, parallelism is employed through the use of multiple execution units that are specialized to handle certain types of operations. Pipelining is also employed in many instances so that certain operations that may take multiple clock cycles to perform are broken up into stages, enabling other operations to be started prior to completion of earlier operations. Multithreading is also employed to enable multiple instruction streams to be processed in parallel, enabling more overall work to performed in any given clock cycle.
One area where parallelism continues to be exploited is in the area of execution units, e.g., fixed point or floating point execution units. Many floating point execution units, for example, are deeply pipelined. However, while pipelining can improve performance, pipelining is most efficient when the instructions processed by a pipeline are not dependent on one another, e.g., where a later instruction does not use the result of an earlier instruction. Whenever an instruction operates on the result of another instruction, typically the later instruction cannot enter the pipeline until the earlier instruction has exited the pipeline and calculated its result. The later instruction is said to be dependent on the earlier instruction, and phenomenon of stalling the later instruction waiting for the result of an earlier instruction is said to introduce “bubbles,” or cycles where no productive operations are being performed, into the pipeline.
One technique that may be used to extract higher utilization from a pipelined execution unit and remove unused bubbles is to introduce multi-threading. In this way, other threads are able to issue instructions into the unused slots in the pipeline, which drives the utilization and hence the aggregate throughput up. Another popular technique for increasing performance is to use a single instruction multiple data (SIMD) architecture, which is also referred to as ‘vectorizing’ the data. In this manner, operations are performed on multiple data elements at the same time, and in response to the same SIMD instruction. A SIMD or vector execution unit typically includes multiple processing lanes that handle different datapoints in a vector and perform similar operations on all of the datapoints at the same time. For example, for an architecture that relies on quad(4)word vectors, an SIMD or vector execution unit may include four processing lanes that perform the identical operations on the four words in each vector.
The aforementioned techniques may also be combined, resulting in a multi-threaded vector execution unit architecture that enables multiple threads to issue SIMD instructions to an SIMD execution unit to process “vectors” of data points at the same time. Typically, a scheduling algorithm is utilized in connection with issue logic to ensure that each thread is able to proceed at a reasonable rate, with the number of bubbles in the execution unit pipeline kept at a minimum.
It has been found, however, that while this configuration is highly desirable for a significant amount of code, there are certain algorithms that are inefficient when executed entirely in an SIMD execution unit, particularly when such algorithms rely on scalar mathematical operations. A conventional SIMD execution unit may be used to perform scalar math; however, only one out of the multiple processing lanes is used, which creates suboptimal performance, and significant underutilization of processing resources.
One such algorithm that incorporates scalar mathematical operations that can result in underutilization of an SIMD execution unit is rasterization, and in particular texture processing performed in a rasterization process. Rasterization is a process in 3D graphics where three dimensional geometry that has been projected onto a screen is “filled in” with pixels of the appropriate color and intensity. A texture mapping algorithm is typically incorporated into a rasterization process to paint a texture onto geometric objects placed into a scene.
In order to paint a texture onto a placed object in a scene, the pixels in each primitive making up the object are typically transformed from 3D scene or world coordinates (e.g., x, y and z) to 2D coordinates relative to a procedural or bitmapped texture (e.g., u and v). The fundamental elements in a texture are referred to as texels (or texture pixels), and being the fundamental element of a texture, each texel is associated with a single color. Due to differences in orientation and distance of the surfaces of placed geometric primitives relative to the viewer, a pixel in an image buffer will rarely correspond to a single texel in a texture. As a result, texture filtering is typically performed to determine a color to be assigned to a pixel based upon the colors of multiple texels in proximity to the texture mapped position of the pixel.
A number of texture filtering algorithms may be used to determine a color for a pixel, including simple interpolation, bilinear filtering, trilinear filtering, and anisotropic filtering, among others. With many texture filtering algorithms, weights are calculated for a number of adjacent texels to a pixel, the weights are used to scale the colors of the adjacent texels, and a color for the pixel is assigned by summing the scaled colors of the adjacent texels. The color is then either stored at the pixel location in a frame buffer, or used to update a color that is already stored at the pixel location.
Colors, which are often represented by multiple data points, e.g., red (R), green (G), blue (B) and alpha (A, representing transparency), are well suited for being represented as vectors and processed in an SIMD execution unit. On the other hand, other operations in a texture mapping algorithm, most notably the calculation of the weights used to determine the color contributions of adjacent texels in a texture to the final color for a pixel, are predominantly scalar operations, and not particularly well suited for calculation in an SIMD execution unit, given that such calculations may leave all but one processing lane of an SIMD execution unit empty. Furthermore, such operations often include dependencies that result in bubbles in the execution pipeline of an SIMD execution unit.
Consequently, certain operations performed in texture processing are not performed efficiently in conventional SIMD execution units. In addition, due to the relatively high computational cost of texture processing, many image processing systems rely on dedicated hardware accelerators in graphics processing units to perform texture processing, foregoing CPU based texture processing due to comparatively inadequate performance.
Therefore, a need exists in the art for a manner of improving texture processing in an SIMD execution unit.